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| NBSG86A 2.5V/3.3V SiGe Differential Smart Gate with Output Level Select The NBSG86A is a multi-function differential Logic Gate which can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1 MUX. This device is part of the GigaCommTM family of high performance Silicon Germanium products. The device is housed in a low profile 4x4 mm, 16-pin, flip-chip BGA or a 3x3 mm 16 pin QFN package. Differential inputs incorporate internal 50 W termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVCMOS/LVTTL, CML, or LVDS. The OLS* input is used to program the peak-to-peak output amplitude between 0 and 800 mV in five discrete steps. The NBSG86A employs input default circuitry so that under open input conditions (Dx, Dx, VTDx, VTDx, VTSEL) the outputs of the device will remain stable. Features http://onsemi.com MARKING DIAGRAM* FCBGA-16 BA SUFFIX CASE 489 16 1 SG 86A LYW 1 QFN-16 MN SUFFIX CASE 485G * Maximum Input Clock Frequency > 8 GHz Typical * * * * * * Maximum Input Data Rate > 8 Gb/s Typical 165 ps Typical Propagation Delay 40 ps Typical Rise and Fall Times Selectable Swing PECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V Selectable Swing NECL Output with NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V Selectable Output Level (0 V, 200 mV, 400 mV, 600 mV, or 800 mV Peak-to-Peak Output) 50 W Internal Input Termination Resistors A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. * * Pb-Free Packages are Available *Output Level Select ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. (c) Semiconductor Components Industries, LLC, 2006 1 July, 2006 - Rev. 10 Publication Order Number: NBSG86A/D CC CC SG 86A ALYWG G NBSG86A 1 A VTD1 2 D1 3 D1 4 VTD1 VTD0 D0 16 OLS 15 D0 14 VTD0 13 Exposed Pad (EP) 12 11 VEE Q Q VCC 1 2 NBSG86A 3 4 B SEL VTSEL VCC Q SEL Q C SEL OLS VEE SEL VTSEL 10 9 D VTD0 D0 D0 VTD0 5 VTD1 6 D1 7 8 D1 VTD1 Figure 1. BGA-16 Pinout (Top View) Table 1. Pin Description Pin BGA C2 C1 QFN 1 2 Name OLS (Note 3) SEL I/O Input ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input - - ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input - - RSECL Output RSECL Output - - ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input - - Figure 2. QFN-16 Pinout (Top View) Description Input Pin for the Output Level Select (OLS). See Table 2. Inverted Differential Select Logic Input. B1 3 SEL Noninverted Differential Select Logic Input. B2 A1 A2 4 5 6 VTSEL VTD1 D1 Common Internal 50 W Termination Pin for SEL/SEL. See Table 7. (Note 1) Internal 50 W termination pin. See Table 7. (Note 1) Noninverted Differential Input 1. Internal 75 kW to VEE. A3 7 D1 Inverted Differential Input 1. Internal 75 kW to VEE and 36.5 kW to VCC. A4 B3 B4 C4 C3 D4 D3 8 9 10 11 12 13 14 VTD1 VCC Q Q VEE VTD0 D0 Internal 50 W Termination Pin. See Table 7. (Note 1) Positive Supply Voltage (Note 2) Noninverted Differential Output. Typically Terminated with 50 W Resistor to VTT = VCC - 2 V. Inverted Differential Output. Typically Terminated with 50 W Resistor to VTT = VCC - 2 V Negative Supply Voltage (Note 2) Internal 50 W Termination Pin. See Table 7. (Note 1) Inverted Differential Input 0. Internal 75 kW to VEE and 36.5 kW to VCC. D2 15 D0 Noninverted Differential Input 0. Internal 75 kW to VEE. D1 N/A 16 - VTD0 EP Internal 50 W Termination Pin. See Table 7. (Note 1) Exposed Pad. The thermally exposed pad on package bottom (see case drawing) must be attached to a heat-sinking conduit. 1. In the differential configuration when the input termination pins (VTDx, VTDx, VTSEL) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self-oscillation. 2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. 3. When an output level of 400 mV is desired and VCC - VEE > 3.0 V, 2 kW resistor should be connected from OLS pin to VEE. http://onsemi.com 2 NBSG86A Table 2. OUTPUT LEVEL SELECT OLS OLS VCC VCC - 0.4 V VCC - 0.8 V VCC - 1.2 V VEE (Note 4) Float Q/Q VPP 800 mV 200 mV 600 mV 0 400 mV 600 mV OLS Sensitivity OLS - 75 mV OLS $ 150 mV OLS $ 100 mV OLS $ 75 mV OLS $ 100 mV N/A 4. When an output level of 400 mV is desired and VCC - VEE > 3.0 V, 2.0 kW resistor should be connected from OLS to VEE. 50 W VTD0 D0 R1 D0 VTD0 50 W 50 W VTD1 D1 R1 D1 VTD1 50 W VTSEL SEL SEL R1 R2 50 W 50 W R1 Q Q R2 Figure 3. Logic Diagram 50 W VTD0 VT or VBB VCC VTD0 VTD1 50 W 50 W D0 D0 Q Q D1 D1 VTD1 50 W 50 W 50 W VEE VCC SEL D0 0 0 0 0 Table 3. AND/NAND TRUTH TABLE (Note 5) m D1 0 0 1 1 b SEL 0 1 0 1 m*b Q 0 0 0 1 m 5. D0, D1, SEL are inverse of D0, D1, SEL unless specified otherwise. VTSEL SEL b Figure 4. Configuration for AND/NAND Function http://onsemi.com 3 NBSG86A 50 W VTD0 m VTD0 50 W 50 W VTD1 VCC VT or VBB VTD1 50 W D0 D0 Q Q D1 D1 50 W 50 W Table 4. OR/NOR TRUTH TABLE** m D0 0 0 1 1 D1 1 1 1 1 b SEL 0 1 0 1 m or b Q 0 1 1 1 ** D0, D1, SEL are inverse of D0, D1, SEL unless specified otherwise. VTSEL SEL b SEL Figure 5. Configuration for OR/NOR Function 50 W VTD0 m VTD0 50 W 50 W VTD1 D0 D0 Q Q D1 D1 Table 5. XOR/XNOR TRUTH TABLE** m D0 0 0 1 50 W 1 D1 1 1 0 0 b SEL 0 1 0 1 m XOR b Q 0 1 1 0 VTD1 50 W 50 W VTSEL SEL ** D0, D1, SEL are inverse of D0, D1, SEL unless specified otherwise. SEL b Figure 6. Configuration for XOR/XNOR Function 50 W VTD0 D0 D0 VTD0 50 W 50 W VTD1 D1 D1 VTD1 50 W 50 W 50 W Q Q Table 6. 2:1 MUX TRUTH TABLE** SEL 1 0 Q D1 D0 ** D0, D1, SEL are inverse of D0, D1, SEL unless specified otherwise. VTSEL SEL SEL Figure 7. Configuration for 2:1 MUX Function http://onsemi.com 4 NBSG86A Table 7. Interfacing Options INTERFACING OPTIONS CML LVDS AC-COUPLED RSECL, PECL, NECL LVTTL, LVCMOS CONNECTIONS Connect VTD0, VTD1, VTSEL and VTD0, VTD1 to VCC Connect VTD0, VTD1, VTD0 and VTD1 together. Leave VTSEL open. Bias VTD0, VTD1, VTSEL and VTD0, VTD1 Inputs within (VIHCMR) Common Mode Range Standard ECL Termination Techniques An external voltage should be applied to the unused complementary differential input. Nominal voltage 1.5 V for LVTTL and VCC/2 for LVCMOS inputs. Table 8. ATTRIBUTES Characteristics Internal Input Pulldown Resistors Internal Input Pullup Resistor ESD Protection (R1) (R2) Human Body Model Machine Model Charged Device Model 16-FCBGA 16-QFN Oxygen Index: 28 to 34 Value 75 kW 37.5 kW > 1 KV > 50 V > 4 KV Level 3 Level 1 UL 94 V-0 @ 0.125 in 364 Moisture Sensitivity (Note 6) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 6. For additional information, see Application Note AND8003/D. Table 9. MAXIMUM RATINGS (Note 7) Symbol VCC VEE VI VINPP IIN Iout TA Tstg qJA Parameter Positive Power Supply Negative Power Supply Positive Input Negative Input Differential Input Voltage |Dn - Dn| Input Current Through RT (50 W Resistor) Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 8) 0 LFPM 500 LFPM 0 LFPM 500 LFPM 2S2P (Note 8) 2S2P (Note 9) < 15 sec < 3 sec @ 248C < 3 sec @ 260C 16 FCBGA 16 FCBGA 16 QFN 16 QFN 16 FCBGA 16 QFN Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V VCC - VEE w 2.8 V VCC - VEE < 2.8 V Static Surge Continuous Surge 16-FCBGA 16-QFN VI v VCC VI w VEE Condition 2 Rating 3.6 -3.6 3.6 -3.6 2.8 |VCC - VEE| 45 80 25 50 -40 to +70 -40 to +85 -65 to +150 108 86 41.6 35.2 5.0 4.0 225 265 265 Units V V V V V V mA mA mA mA C C C C/W C/W C/W C/W C/W C/W C qJC Tsol Thermal Resistance (Junction-to-Case) Wave Solder Pb (BGA) Pb (QFN) Pb-Free (QFN) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 7. Maximum Ratings are those values beyond which device damage may occur. 8. JEDEC standard multilayer board - 2S2P (2 signal, 2 power). 9. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 5 NBSG86A Table 10. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 10) -40C Symbol IEE VOH VOL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 11) Output LOW Voltage (Note 11) (OLS = VCC) (OLS = VCC - 0.4 V) (OLS = VCC - 0.8 V, OLS = FLOAT) (OLS = VCC - 1.2 V) (OLS = VEE) Output Voltage Amplitude (OLS = VCC) (OLS = VCC - 0.4 V) (OLS = VCC - 0.8 V, OLS = FLOAT) (OLS = VCC - 1.2 V) (OLS = VEE) VIH VIL VIHCMR Input HIGH Voltage (Single-Ended) (Note 13) D, D Input LOW Voltage (Single-Ended) (Note 14) D, D Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 12) Internal Input Termination Resistor Input HIGH Current (@VIH) Input LOW Current (@VIL) D, D SEL D, D SEL 670 125 510 0 325 VEE + 1275 VEE 1.2 800 215 615 5 415 VCC - 1000* VCC- 1400* VCC VIH- 150 2.5 660 120 505 0 320 VEE + 1275 VEE 1.2 795 210 610 0 410 VCC - 1000* VCC- 1400* VCC VIH- 150 2.5 655 120 500 0 320 VEE + 1275 VEE 1.2 790 210 605 5 410 VCC- 1000* VCC- 1400* VCC VIH- 150 2.5 mV mV V Min 23 1460 555 1235 775 1455 1005 Typ 30 1510 705 1295 895 1505 1095 Max 39 1560 855 1385 1015 1585 1215 Min 23 1490 595 1270 810 1490 1040 25C Typ 30 1540 745 1330 930 1540 1130 Max 39 1590 895 1420 1050 1620 1250 70C(BGA)/85C(QFN)** Min 23 1515 625 1295 840 1510 1065 Typ 30 1565 775 1355 960 1560 1155 Max 39 1615 925 1445 1080 1640 1275 mV Unit mA mV mV VOUTPP RTIN IIH IIL 45 50 30 5 20 5 55 100 50 100 50 45 50 30 5 20 5 55 100 50 100 50 45 50 30 5 20 5 55 100 50 100 50 W mA mA NOTE: GigaComm circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 10. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -0.965 V. 11. All loading with 50 W to VCC - 2.0 V. 12. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 13. VIH cannot exceed VCC. 14. VIL always w VEE. *Typicals used for testing purposes. **The device packaged in FCBGA-16 have maximum ambient temperature specification of 70C and devices packaged in QFN-16 have maximum ambient temperature specification of 85C. http://onsemi.com 6 NBSG86A Table 11. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 15) -40C Symbol IEE VOH VOL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 16) Output LOW Voltage (Note 16) (OLS = VCC) (OLS = VCC - 0.4 V) (OLS = VCC - 0.8 V, OLS = FLOAT) (OLS = VCC - 1.2 V) **(OLS = VEE) Output Amplitude Voltage (OLS = VCC) (OLS = VCC - 0.4 V) (OLS = VCC - 0.8 V, OLS = FLOAT) (OLS = VCC - 1.2 V) **(OLS = VEE) VIH VIL VIHCMR Input HIGH Voltage (Single-Ended) (Note 18) D, D Input LOW Voltage (Single-Ended) (Note 19) D, D Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 17) Internal Input Termination Resistor Input HIGH Current (@VIH) Input LOW Current (@VIL) D, D SEL D, D SEL 705 130 535 0 345 VEE + 1275 VIH- 2600 1.2 815 220 640 0 435 VCC - 1000* VCC- 1400* VCC VIH- 150 3.3 695 125 530 0 340 VEE + 1275 VIH- 2600 1.2 805 215 635 0 430 VCC - 1000* VCC- 1400* VCC VIH- 150 3.3 690 125 525 0 335 VEE + 1275 VIH- 2600 1.2 800 215 630 0 425 VCC - 1000* VCC- 1400* VCC VIH- 150 3.3 mV mV V Min 23 2260 1320 2030 1550 2260 1785 Typ 30 2310 1470 2090 1670 2310 1875 Max 39 2360 1620 2180 1790 2390 1995 Min 23 2290 1360 2065 1585 2290 1820 25C Typ 30 2340 1510 2125 1705 2340 1910 Max 39 2390 1660 2215 1825 2420 2030 70C(BGA)/85C(QFN)*** Min 23 2315 1390 2090 1615 2315 1850 Typ 30 2365 1540 2150 1735 2365 1940 Max 39 2415 1690 2240 1855 2445 2060 mV Unit mA mV mV VOUTPP RTIN IIH IIL 45 50 30 5 20 5 55 100 50 100 50 45 50 30 5 20 5 55 100 50 100 50 45 50 30 5 20 5 55 100 50 100 50 W mA mA NOTE: GigaComm circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 15. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.165 V. 16. All loading with 50 W to VCC - 2.0 V. 17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 18. VIH cannot exceed VCC. 19. VIL always w VEE. *Typicals used for testing purposes. **When an output level of 400 mV is desired and VCC - VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE. ***The device packaged in FCBGA-16 have maximum ambient temperature specification of 70C and devices packaged in QFN-16 have maximum ambient temperature specification of 85C. http://onsemi.com 7 NBSG86A Table 12. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT VCC = 0 V; VEE = -3.465 V to -2.375 V (Note 20) -40C Symbol IEE VOH VOL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 21) Output LOW Voltage (Note 21) -3.465 V v VEE v -3.0 V (OLS = VCC) (OLS = VCC - 0.4 V) (OLS = VCC - 0.8 V, OLS =FLOAT) (OLS = VCC - 1.2 V) **(OLS = VEE) -3.0 V < VEE v -2.375 V (OLS = VCC) (OLS = VCC - 0.4 V) (OLS = VCC - 0.8 V, OLS =FLOAT) (OLS = VCC - 1.2 V) (OLS = VEE) Output Voltage Amplitude -3.465 V v VEE v -3.0 V (OLS = VCC) (OLS = VCC - 0.4 V) (OLS = VCC - 0.8 V, OLS = FLOAT) (OLS = VCC - 1.2 V) **(OLS = VEE) -3.0 V < VEE v -2.375 V (OLS = VCC) (OLS = VCC - 0.4 V) (OLS = VCC - 0.8 V, OLS =FLOAT) (OLS = VCC - 1.2 V) (OLS = VEE) Input HIGH Voltage (Single-Ended) (Note 23) D, D Input LOW Voltage (Single-Ended) (Note 24) D, D Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 22) Internal Input Termination Resistor Input HIGH Current (@VIH) Input LOW Current (@VIL) D, D SEL D, D SEL Min 23 -1040 Typ 30 -990 Max 39 -940 Min 23 -1010 25C Typ 30 -960 Max 39 -910 70C(BGA)/85C(QFN)*** Min 23 -985 Typ 30 -935 Max 39 -885 Unit mA mV mV -1980 -1270 -1750 -1040 -1515 -1945 -1265 -1725 -1045 -1495 -1830 -1210 -1630 -990 -1425 -1795 -1205 -1605 -995 -1405 -1680 -1120 -1510 -910 -1305 -1645 -1115 -1485 -915 -1285 -1940 -1235 -1715 -1010 -1480 -1905 -1230 -1690 -1010 -1460 -1790 -1175 -1595 -960 -1390 -1755 -1170 -1570 -960 -1370 -1640 -1085 -1475 -880 -1270 -1605 -1080 -1450 -880 -1250 -1910 -1210 -1685 -985 -1450 -1875 -1205 -1660 -990 -1435 -1760 -1150 -1565 -935 -1360 -1725 -1145 -1540 -940 -1345 -1610 -1060 -1445 -855 -1240 -1575 -1055 -1420 -860 -1225 mV 705 130 535 0 345 670 125 510 0 325 VEE + 1275 VIH- 2600 815 220 640 0 435 800 215 615 5 415 VCC - 1000* VCC- 1400* VCC VIH- 150 0.0 695 125 530 0 340 660 120 505 0 320 VEE + 1275 VIH- 2600 805 215 635 0 430 795 210 610 0 410 VCC - 1000* VCC- 1400* VCC VIH- 150 0.0 690 125 525 0 335 655 120 500 0 320 VEE + 1275 VIH- 2600 800 215 630 0 425 790 210 605 5 410 VCC - 1000* VCC- 1400* VCC VIH- 150 0.0 mV mV V VOUTPP VIH VIL VIHCMR VEE+1.2 VEE+1.2 VEE+1.2 RTIN IIH IIL 45 50 30 5 20 5 55 100 50 100 50 45 50 30 5 20 5 55 100 50 100 50 45 50 30 5 20 5 55 100 50 100 50 W mA mA NOTE: GigaComm circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 20. Input and output parameters vary 1:1 with VCC. 21. All loading with 50 W to VCC - 2.0 V. 22. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 23. VIH cannot exceed VCC. 24. VIL always w VEE. *Typicals used for testing purposes. **When an output level of 400 mV is desired and VCC - VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE. ***The device packaged in FCBGA-16 have maximum ambient temperature specification of 70C and devices packaged in QFN-16 have maximum ambient temperature specification of 85C. http://onsemi.com 8 NBSG86A Table 13. AC CHARACTERISTICS for FCBGA-16 VCC = 0 V; VEE = -3.465 V to -2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V -40C Symbol fmax VOUTPP tPLH, tPHL tSKEW tSKEW tJITTER Characteristic Maximum Frequency (See Figure 8) (Note 25) Output Voltage Amplitude (OLS = VCC) fin v 7 GHz Min 7 Typ 8 Max Min 7 25C Typ 8 Max Min 7 70C Typ 8 Max Unit GHz 550 110 740 160 5 210 15 20 500 115 720 165 5 5 215 15 20 450 120 700 170 5 5 220 15 20 mV ps ps ps ps Propagation Delay to Output Differential D/SEL Q Duty Cycle Skew (Note 26) Channel Skew RMS Random Clock Jitter (See Figure 8) (Note 25) Q D/SEL 5 fin v 7 GHz Peak-to-Peak Data Dependent Jitter fin v 7 Gb/s 75 (Q, Q) 20 0.5 12 1.5 0.5 12 1.5 0.5 12 1.5 VINPP tr tf Input Voltage Swing/Sensitivity (Differential Configuration) (Note 27) Output Rise/Fall Times (20% - 80%) @ 1 GHz 2600 75 2600 75 2600 mV ps 40 65 20 40 65 20 40 65 25. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. Input edge rates 40 ps (20% - 80%). 26. tSKEW = |tPLH - tPHL| for a nominal 50% differential clock input waveform. See Figure 12. 27. VINPP (max) cannot exceed VCC - VEE. Table 14. AC CHARACTERISTICS for QFN-16 VCC = 0 V; VEE = -3.465 V to -2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V -40C Symbol fmax VOUTPP tPLH, tPHL tSKEW tSKEW tJITTER Characteristic Maximum Frequency (See Figure 8) (Note 28) Output Voltage Amplitude (OLS = VCC) fin v 7 GHz fin = 8 GHz Min 7 590 270 110 Typ 8 730 440 160 5 Q D/SEL 5 210 15 20 Max Min 7 470 230 115 25C Typ 8 720 420 165 5 5 215 15 20 Max Min 7 540 180 120 85C Typ 8 700 390 170 5 5 220 15 20 ps ps ps 0.5 12 75 (Q, Q) tr tf 2600 75 1.5 0.5 12 2600 75 1.5 0.5 12 2600 mV ps 30 17 45 35 60 65 30 17 45 35 60 65 30 17 45 35 60 65 1.5 Max Unit GHz mV mV ps Propagation Delay to Output Differential D/SEL Q Duty Cycle Skew (Note 29) Channel Skew RMS Random Clock Jitter (See Figure 8) (Note 31) fin v 7 GHz Peak-to-Peak Data Dependent Jitter (Note 32) fin v 7 Gb/s VINPP tr tf Input Voltage Swing/Sensitivity (Differential Configuration) (Note 30) Output Rise/Fall Times (20% - 80%) @ 1 GHz 28. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. Input edge rates 40 ps (20% - 80%). 29. tSKEW = |tPLH - tPHL| for a nominal 50% differential clock input waveform. See Figure 12. 30. VINPP (max) cannot exceed VCC - VEE. 31. Additive RMS jitter with 50% duty cycle clock signal at 7 GHz. 32. Additive Peak-to-Peak data dependent jitter with NRZ PRBS 231-1 data rate at 7 Gb/s. http://onsemi.com 9 NBSG86A 900 OUTPUT VOLTAGE AMPLITUDE (mV) 800 700 600 500 *OLS = VEE 400 300 200 100 RMS JITTER 0 0 1 2 3 4 5 6 7 8 9 0 10 OLS = VCC - 0.4 V 4 3 2 1 OLS = VCC OLS = VCC - 0.8 V, OLS = FLOAT 9 8 JITTEROUT ps (RMS) JITTEROUT ps (RMS) 7 6 5 INPUT FREQUENCY (GHz) Figure 8. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) for 2:1 MUX Mode (VCC - VEE = 2.5 V @ 255C; Repetitive 1010 Input Data Pattern) 900 OUTPUT VOLTAGE AMPLITUDE (mV) 800 700 600 500 400 300 200 100 RMS JITTER 0 0 1 2 3 4 5 6 7 8 9 *OLS = VEE OLS = VCC - 0.8 V OLS = FLOAT OLS = VCC 9 8 7 6 5 4 3 2 1 0 10 OLS = VCC - 0.4 V INPUT FREQUENCY (GHz) Figure 9. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) for 2:1 MUX Mode (VCC - VEE = 3.3 V @ 255C; Repetitive 1010 Input Data Pattern) *When an output level of 400 mV is desired and VCC - VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE. http://onsemi.com 10 NBSG86A 300 200 100 0 IOLS (mA) -100 -200 -300 -400 -500 -600 -700 VCC VCC - 400 VCC - 800 VOLS (mV) VCC - 1200 VEE Figure 10. Typical OLS Input Current vs. OLS Input Voltage (VCC - VEE = 3.3 V @ 255C) 1000 VCC - 75 800 VCC - 700 600 VEE + 100 400 VCC - 250 200 VCC - 1125 0 VCC VCC - 400 VCC - 800 OLS (mV) VCC - 1200 VEE VCC - 1275 VCC - 550 VCC - 900 VOUTPP (mV) Figure 11. OLS Operating Area http://onsemi.com 11 NBSG86A D D Q Q tPLH VINPP(D) = VIH(D) - VIL(D) VINPP(D) = VIH(D) - VIL(D) VOUTPP(Q) = VOH(Q) - VOL(Q) VOUTPP(Q) = VOH(Q) - VOL(Q) tPHL Figure 12. AC Reference Measurement Q Driver Device Q Z = 50 W D Receiver Device Z = 50 W 50 W 50 W D V TT V TT = V CC - 2.0 V Figure 13. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020 - Termination of ECL Logic Devices) ORDERING INFORMATION Device NBSG86ABA NBSG86ABAR2 NBSG86AMN NBSG86AMNG Package Type 4x4 mm FCBGA-16 4x4 mm FCBGA-16 3x3 mm QFN-16 3x3 mm QFN-16 (Pb-Free) 3x3 mm QFN-16 3x3 mm QFN-16 (Pb-Free) Shipping 100 Units / Tray (Contact Sales Representative) 100 / Tape & Reel 123 Units / Rail 123 Units / Rail NBSG86AMNR2 NBSG86AMNR2G 3000 / Tape & Reel 3000 / Tape & Reel Board NBSG86ABAEVB Description NBSG86ABA Evaluation Board For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 12 NBSG86A PACKAGE DIMENSIONS FCBGA-16 BA SUFFIX PLASTIC 4 X 4 (mm) BGA FLIP CHIP PACKAGE CASE 489-01 ISSUE O LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA -X- D M NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. DIM A A1 A2 b D E e S MILLIMETERS MIN MAX 1.40 MAX 0.25 0.35 1.20 REF 0.30 0.50 4.00 BSC 4.00 BSC 1.00 BSC 0.50 BSC -Y- K E M 0.20 3X FEDUCIAL FOR PIN A1 IDENTIFICATION IN THIS AREA A B C D e 4 3 2 1 3 16 X b 0.15 0.08 M M S VIEW M-M ZXY Z 5 0.15 Z A A2 -Z- A1 16 X 4 DETAIL K 0.10 Z ROTATED 90 _ CLOCKWISE http://onsemi.com 13 NBSG86A PACKAGE DIMENSIONS 16 PIN QFN CASE 485G-01 ISSUE C D A B PIN 1 LOCATION E NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 0.15 C 0.15 C 0.10 C TOP VIEW 16 X 0.08 C SIDE VIEW A1 C 16X L 5 NOTE 5 4 16X K 1 12 16X b BOTTOM VIEW 0.50 0.02 0.30 0.012 SCALE 10:1 mm inches 0.10 C A B 0.05 C NOTE 3 GigaComm is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative CC CC CC (A3) D2 e 8 9 16 13 A SEATING PLANE DIM A A1 A3 b D D2 E E2 e K L SOLDERING FOOTPRINT* 3.25 0.128 0.30 0.012 EXPOSED PAD 0.575 0.022 EXPOSED PAD E2 e 3.25 0.128 1.50 0.059 *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 14 NBSG86A/D |
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